(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of selectively forming of low-voltage metal gate electrode in addition to forming a high-voltage polysilicon gate electrode.
(2) Description of the Prior Art
Conventional methods of creating CMOS devices use gate electrodes of polysilicon that is deposited and patterned over a layer of gate oxide. In many applications the surface of the patterned and etched layer of polysilicon is salicided in order to meet requirements of low contact sheet resistivity. With the continued decrease in device and device feature dimensions, the polysilicon of the gate electrode is more prone to depletion of the polysilicon, which results in a significant reduction in device performance. Polysilicon depletion results in increased resistivity of the layer of polysilicon, which in turn results in an increase of the voltage drop across the polysilicon gate electrode when this electrode is reverse mode biased. To address and largely negate this problem and in view of the fact that metal is a good conductor, the industry in increasingly turning to the use of metal to create gate electrodes. Metal however is susceptible to migration to surrounding regions under conditions of elevated temperature that can arise during the process of creating the CMOS device. The gate length of CMOS devices is the distance between the source and the drain regions of the device where this distance extends underneath the gate electrode. With the continued decrease in device dimensions, the gate length for sub-micron devices has been decreased to 0.25 μm or less. For such small gate length, the control of the Critical Dimension (CD) of this parameter becomes a challenge. To address this aspect of metal gate electrode design, the approach has been provided whereby a dummy gate is first created. This dummy gate uses a dielectric, such as silicon dioxide or a polymer, for the body of the gate. The area surrounding the gate electrode is shielded by the deposition of a layer of for instance oxide, an opening is created in this layer of oxide that aligns with the surface of the gate electrode after which the dummy gate is removed. The opening that is created in this manner can now be filled with new dielectrics first, for instance silicon dioxide or other high-k material, and filled with metal. Polishing of the surface of the deposited metal completes the creation of the sub-micron metal gate electrode.
As previously stated, the integration of metal as the material of choice for the formation of high performance gate electrodes is required in order to reduce the depletion of gate polysilicon. This integration of metal requires a gate replacement process. However, current logic application requires the use of different oxide thicknesses, typically limited to two thicknesses, for the creation of the gate dielectric underlying the gate electrode. Core CMOS applications, which constitute the majority of the CMOS devices that are being created, require high switching speeds, which imposes the requirement of having a thin layer of gate dielectric. Also created however are Input/Output devices, which are required to provide drive currents of relatively large values, which imposes the requirement of having a relatively thick layer of gate dielectric. The requirement of simultaneously creating CMOS devices of different gate dielectric thicknesses may lead to two separate damascene processes whereby each of these two processes provides for one thickness of the gate dielectric. The invention addresses this concern and provides a method for forming a metal gate electrode having a thin layer of gate dielectric, for high-performance application of CMOS devices. The low-voltage metal gate electrode of the invention is created over the surface of a substrate over which high-voltage gate electrodes are simultaneously created.
U.S. Pat. No. 6,087,231 (Xiang et al.) shows a process for a dual gate.
U.S. Pat. No. 6,159,782 (Xiang et al.), U.S. Pat. No. 5,960,270 (Misra et al.) and U.S. Pat. No. 6,043,157 (Gardner et al.) reveal processes for dual gates and dummy gates.